1. Field of the Invention
The invention relates to a frequency synthesizer comprising a first input for receiving a first frequency signal and a second input for receiving a second frequency signal, a comparator coupled to the first and second inputs for comparing the first and second signals, and charging means having an input coupled to an output of said comparator, and an output coupled to an output of the frequency synthesizer for supplying an output signal.
The invention further relates to a receiver comprising such a frequency synthesizer.
2. Description of the Related Art
Such frequency synthesizers are known and can be used for down conversion of RF signals in a digital or analog satellite receiver, car radios, digital or analog (cable) TV receivers, cordless or wireless telephones, etc.
By combining the voltage-controlled oscillator of the phase-locked loop demodulator with the voltage-controlled oscillator of the frequency synthesizer, a major cost reduction can be achieved in systems wherein direct demodulation of FM signals is employed.
Such a receiver is, for example, known from U.S. Pat. No. 5,446,411, wherein a phase-locked loop is used as an FM demodulator. The frequency synthesizer is used to set up the phase-locked loop demodulator to run at a predetermined frequency. A standard PLL frequency synthesizer is not suitable in systems were the tuning voltage-controlled oscillator is used for demodulation.
The reason is that two PLLs, the frequency synthesizer and the demodulation loop (FM) or the synchronization loop (AM), will try to lock the same VCO to different frequencies (the former to the multiplied crystal, and the latter to the carrier frequency), which leads to a non-functional system. To overcome the is disadvantages mentioned above, the output of the frequency synthesizer is coupled, via switching means and a resistive divider, to the input of the voltage-controlled oscillator.
Disadvantages of this frequency synthesizer is that the switching means at the output of the frequency synthesizer can cause transients, loss of lock, and spikes during switching. Further, such a resistive divider has thermal noise. Power dissipation is high due to the presence of a frequency measurement device operating at the highest frequency.
An object of the invention is to overcome the disadvantages of the prior art and further to provide a frequency synthesizer with lower costs, lower dissipation, lower noise, and with an improved performance and wider application range.
To this end a first aspect of the invention provides a frequency synthesizer as described in the opening paragraph, characterized in that the frequency synthesizer further comprises a frequency window detector also coupled to the first and second inputs, said frequency window detector supplying an output signal depending on whether or not the first and second frequency signals are within a predetermined frequency window, and switching means coupled between the comparator and the charging means, said switching means being controlled by the output signal of the frequency window detector. A second aspect of the invention provides a receiver incorporating such frequency synthesizer.
The invention is-based on the recognition that by using a frequency window detector and switching means between the comparator and the charging means, the frequency synthesizer can be turned off. There are two ways to implement this. Firstly, its effect is zero, but the circuitry stays active (watch dog function), and secondly, completely xe2x80x9cturn offxe2x80x9d (low power dissipation). In this way, the influence of the frequency synthesizer during normal operation, that is, within the frequency window, is reduced to (nearly) zero. Because the switching means is turned off before the charging means, at the moment when the charging means becomes inactive, no transients or spikes can occur at the output of the frequency synthesizer.
A further advantage of the frequency synthesizer according to the invention is that the accuracy of the frequency of the output signal is not dependent on the accuracy of the reference frequency.
This receiver structure, with the combined tuning system, enables the use of cheap crystal oscillators because when the voltage-controlled oscillator is xe2x80x9cin-windowxe2x80x9d, the frequency synthesizer is disabled. Therefore, the accuracy of the VCO frequency is not dependent on the accuracy of the crystal frequency, but on the Automatic Frequency Control (AFC). Another advantage is that the AFC has taken over control of the VCO, saving a substantial amount of power dissipation when switching off the power of the frequency synthesizer.
It is to be noted here that from U.S. Pat. No. 4,787,097, a phase-locked loop having a phase detector and a frequency detector, with associated monitor and recovery circuitry, is known for data and clock extraction from NRZ (Non Return to Zero) data streams. After detecting that the phase-locked loop is outside a narrow frequency window, the phase detector is turned off and the frequency detector is turned on. After determining that the phase-locked loop is (again) within the narrow frequency window, the phase detector is turned on and the frequency detector is turned off. Further, this phase-locked loop comprises an EXOR (exclusive OR) and analog elements to obtain a first input signal for the phase-frequency comparator.
The frequency synthesizer of the invention contains no analog elements and is therefore robust with relation to aging, spread in component values, etc.
An embodiment of a frequency synthesizer according to the invention is characterized in that the frequency synthesizer comprises a first divider for dividing the first frequency input signal by a first predetermined value, and a second divider for dividing the second frequency input signal by a second predetermined value.
The division values of the dividers can be chosen depending on the input signals and/or on the crystal oscillator used.
Another embodiment of a frequency synthesizer according to the invention is characterized in that the frequency window detector comprises a logic circuit having inputs coupled, respectively, to the first and the second inputs of the frequency synthesizer, and an output, a phase-frequency detector for supplying a frequency,.difference signal, said phase-frequency detector having a first input coupled to the output of the logic circuit, a second input and an output, and a programmable divider having an input coupled to the second input of the frequency synthesizer, and an output coupled to the second input of the phase-frequency detector, said phase-frequency detector supplying an output signal depending on a frequency difference between the first and second frequency signals as a control signal to the switching means.
In this way, the switching signal for the switching means is obtained very efficiently.
A further embodiment of a frequency synthesizer according to the invention is characterized in that the logic circuit comprises a first D-Flip-Flop having inputs coupled, respectively, to the first and second inputs of the frequency synthesizer, and an output, a multiplexer having a first input coupled to the output of the first D-Flip-Flop, a second input, a select input, and an output, a second D-Flip-Flop having a first input coupled to the first input of the frequency synthesizer, a second input, and an output, an OR-gate having a first input coupled to the second input of the frequency synthesizer, a second input coupled to receive a clock signal, and an output coupled to the second input of the second D-Flip-Flop, an EXOR-gate having a first input coupled to the output of the second D-Flip-Flop, a second input coupled to the output of the first D-Flip-Flop, and an output coupled to the select input of the multiplexer, and a third D-Flip-Flop having a first input coupled to the output of the multiplexer, a second input coupled to the second input of the frequency synthesizer, and an output coupled to the second input of the multiplexer and to the phase-frequency detector.
To further improve the switching signal, the logic circuit of the frequency window detector comprises three D-Flip-Flops to overcome possible unwanted (extra) switching signals.
The invention and additional features, which may optionally be used to implement the invention to advantage, will be apparent from and elucidated with reference to the examples described below hereinafter and shown in the figures, in which:
FIG. 1 shows a block schematic example of a frequency synthesizer according to the invention;
FIG. 2 shows a block schematic example of a frequency synthesizer in more-detail according to the invention;
FIG. 3 shows a block schematic example of a receiver comprising a frequency synthesizer according to the invention;
FIG. 4 shows a block schematic example of a receiver comprising a frequency synthesizer according to the invention;
FIG. 5 shows a block schematic example of a receiver comprising a frequency synthesizer according to the invention; and
FIG. 6 shows a block schematic example of a frequency window detector according to the invention.
Throughout the description, corresponding elements will have corresponding reference numerals.